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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
256K x 72 Bit BurstRAM Multichip Module
The 256K x 72 multichip module uses four 4M bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPCTM and other high performance microprocessors. It is organized as 256K words of 72 bits each. This device integrates input registers, an output register (MCM72PB8ML only), a 2-bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and linear burst order (LBO) are clock (K) controlled through positive- edge-triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The eight bytes are designated as "a" through "h". SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. The module can be configured as either a pipelined or flow-through SRAM. For read cycles, pipelined SRAMs output data is temporarily stored by an edge- triggered output register and then released to the output buffers at the next rising edge of clock (K). Flow-through SRAMs allow output to simply flow freely from the memory array. The multichip module operates from a 3.3 V core power supply and all outputs operate on a separate 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. * 3.3 V + 10%, - 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply * ADSP, ADSC, and ADV Burst Control Pins * Option for Pipeline or Flow-Through (Speeds Guaranteed When Module is Purchased by Appropriate Part Number) * Selectable Burst Sequencing Order (Linear/Interleaved) * Single-Cycle Deselect Timing * Internally Self-Timed Write Cycle * Byte Write and Global Write Control * JEDEC BGA Pin Assignment
MCM72FB8ML MCM72PB8ML
MULTICHIP MODULE PBGA CASE 1103B-01
PIN A1 INDICATION (corner without fiducial)
TOP VIEW
PIN A1 BOTTOM VIEW INDICATION (corner with (Drawings Not to Scale) fiducial)
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 7/30/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML 1
256K X 72 FOUR-CHIP MODULE BLOCK DIAGRAM
18 MCM69P/F819DC* SA2 - SA17 SA0 LW SA1 DQ0 - DQ8 ADSP ADSC UW ADV DQ9 - DQ17 K G SE1 SE2 SE3 LBO SW SGW FT MCM69P/F819DC* SA2 - SA17 SA0 LW SA1 DQ0 - DQ8 ADSP ADSC UW ADV DQ9 - DQ17 K G SE1 SE2 SE3 LBO SW SGW FT MCM69P/F819DC* SA2 - SA17 SA0 LW SA1 DQ0 - DQ8 ADSP ADSC UW ADV DQ9 - DQ17 K G SE1 SE2 SE3 LBO SW SGW FT MCM69P/F819DC* SA2 - SA17 SA0 LW SA1 DQ0 - DQ8 ADSP ADSC UW ADV DQ9 - DQ17 K G SE1 SE2 SE3 LBO SW SGW FT * Motorola TrueDie devices.
SA2 - SA17 SA0 SA1 ADSP ADSC ADV K G SE1 SE2 SE3 LBO SW SGW FT
SBa
9
DQa
SBb
9
DQb
SBc
9
DQc
SBd
9
DQd
SBe
9
DQe
SBf
9
DQf
SBg
9
DQg
SBh
9
DQh
MCM72FB8ML MCM72PB8ML 2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
5 A B C D E DQe F G DQf H J K L M DQg N P R T DQh U V DQh W DQh DQh DQh NC NC SA NC SA NC SA0 NC SA NC SA NC NC NC DQa DQa DQa DQa DQh DQh DQh VDDQ VDD LBO VSS SW VSS VDD VDDQ DQa DQa DQa DQa VDDQ VDDQ SA1 VDDQ VDDQ FT DQg DQg DQg DQg DQg DQg DQh VDDQ VSS VDDQ VDD VDDQ VDD VDDQ VDD VSS VSS VSS VSS VSS VSS NC K VSS VSS VSS VSS VSS VDD VDD VDD VDDQ DQb VDDQ DQb VDDQ DQb VDDQ DQa DQb DQb DQb DQb DQf DQf SBf DQg DQf VDDQ VDD DQf VDDQ VSS DQf SBg DQg SBe NC SBh VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDDQ DQc VSS VDDQ VSS VSS VSS SBd NC SBa DQc DQc SBb DQb DQc DQc DQc SBc DQb DQf DQf VDDQ VDD DQf VDDQ VDD VSS ADSC VSS VSS ADSP VSS VDD VDD VDDQ DQc VDDQ DQc DQd DQc DQe DQe DQe DQe 6 DQe DQe DQe 7 SA SA 8 SA SA 9 SA SA 10 SE1 G 11 SA SA 12 SA SA 13 SA SA 14 DQd DQd DQd 15 DQd DQd DQd DQd
SE2 VDDQ VDDQ SGW VDDQ VDDQ SE3 VSS ADV VSS
DQe VDDQ VDD
VDD VDDQ DQd
TOP VIEW 256K X 72 JEDEC FOUR-CHIP MODULE 209 BUMP PBGA Not to Scale
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML 3
PIN DESCRIPTIONS
Pin Locations E10 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate READ, WRITE, or chip deselect cycle. Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate READ, WRITE, or chip deselect cycle (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b, c, d, e, f, g, h).
F10
ADSP
Input
D10 (a) R14, T14, T15, U14, U15, V14, V15, W14, W15 (b) L14, L15, M14, M15, N14, N15, P14, P15, R15 (c) E14, F14, F15, G14, G15, H14, H15, J14, J15 (d) A14, A15, B14, B15, C14, C15, D14, D15, E15 (e) A5, A6, B5, B6, C5, C6, D5, D6, E5 (f) E6, F5, F6, G5, G6, H5, H6, J5, J6 (g) L5, L6, M5, M6, N5, N6, P5, P6, R5 (h) R6, T5, T6, U5, U6, V5, V6, W5, W6 U13
ADV DQx
Input I/O
FT
Input
Flow-Through Input: This pin must remain in steady state (this signal is not registered or latched). It must be tied high or low. Low -- flow-through mode. High -- pipeline mode. Asynchronous Output Enable. Clock: This signal registers the address, data in, and all control signals except G, LBO, and FT. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst counter (68K/PowerPC). High -- interleaved burst counter (486/i960/Pentium). Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b, c, d, e, f, g, h). SGW overrides SBx. Synchronous Chip Enable: Active low to enable chip. Negated high-blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Core Power Supply. I/O Power Supply.
B10 R10 U7
G K LBO
Input Input Input
U10, V10
SA1, SA0
Input
A7, A8, A9, A11, A12, A13, B7, B8, B9, B11, B12, B13, V8, V9, V11, V12 L13, K14, K15, J13, J7, K5, K6, L7 (a) (b) (c) (d) (e) (f) (g) (h) A10
SA2 - SA17 SBx SE1
Input Input Input
C7 C13 C10
SE2 SE3 SGW
Input Input Input
T10
SW
Input
D8, D12, E8, E12, F8, F12, G8, G12, N8, N12, P8, P12, R8, R12, T8, T12 C8, C9, C11, C12, D7, D13, E7, E13, F7, F13, G7, G13, H7, H13, M7, M13, N7, N13, P7, P13, R7, R13, T7, T13, U8, U9, U11, U12
VDD VDDQ
Supply Supply
MCM72FB8ML MCM72PB8ML 4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS (continued)
Pin Locations D9, D11, E9, E11, F9, F11, G9 - G11, H8 - H12, J8 - J12, K8 - K12, L8 - L12, M8 - M12, N9 - N11, P9, P11, R9, R11, T9, T11 K7, K13, P10, V7, V13, W7 - W13 Symbol VSS Type Supply Ground. Description
NC
--
No Connection: There is no connection to the chip.
TRUTH TABLE (See Notes 1 through 5)
Next Cycle Deselect Deselect Deselect Deselect Deselect Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Continue Write Continue Write Suspend Write Suspend Write Address Used None None None None None External External Next Next Next Next Current Current Current Current External Next Next Current Current SE1 1 0 0 X X 0 0 X X 1 1 X X 1 1 0 X 1 X 1 SE2 X X 0 X 0 1 1 X X X X X X X X 1 X X X X SE3 X 1 X 1 X 0 0 X X X X X X X X 0 X X X X ADSP X 0 0 1 1 0 1 1 1 X X 1 1 X X 1 1 X 1 X ADSC 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 0 1 1 1 1 ADV X X X X X X X 0 0 0 0 1 1 1 1 X 0 0 1 1 G3 X X X X X X X 1 0 1 0 1 0 1 0 X X X X X DQx High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DQ High-Z DQ High-Z DQ High-Z DQ High-Z High-Z High-Z High-Z High-Z Write 2, 4 X X X X X X5 READ5 READ READ READ READ READ READ READ READ WRITE WRITE WRITE WRITE WRITE
NOTES: 1. X = Don't Care. 1 = logic high. 0 = logic low. 2. Write is defined as either 1) any SBx and SW low or 2) SGW is low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times. 5. This read assumes the RAM was previously deselected.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X10 X . . . X11 X . . . X00 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML 5
WRITE TRUTH TABLE
Cycle Type Read Read Write Byte a Write Byte b Write Byte c Write Byte d Write Byte e Write Byte f Write Byte g Write Byte h Write All Bytes Write All Bytes SGW H H H H H H H H H H H L SW H L L L L L L L L L L X SBa X L L H H H H H H H L X SBb X H H L H H H H H H L X SBc X H H H L H H H H H L X SBd X H H H H L H H H H L X SBe X H H H H H L H H H L X SBf X H H H H H H L H H L X SBg X H H H H H H H L H L X SBh X H H H H H H H H L L X
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Power Supply Voltage I/O Supply Voltage Input Voltage Relative to VSS for Any Pin Except VDD Input Voltage (Three-State I/O) Output Current (per I/O) Package Power Dissipation Ambient Temperature Die Temperature Temperature Under Bias Storage Temperature Symbol VDD VDDQ Vin, Vout VIT Iout PD TA TJ Tbias Tstg Value VSS - 0.5 to + 4.6 VSS - 0.5 to VDD VSS - 0.5 to VDD + 0.5 VSS - 0.5 to VDDQ + 0.5 20 6.4 0 to 70 110 - 10 to 85 - 55 to 125 Unit V V V V mA W C C C C 3 3 2 2 2 Notes This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. This is a steady-state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing is not necessary. 3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Single-Layer Board Four-Layer Board Symbol RJA RJB RJC Max 19 13 10 0.3 Unit C/W C/W C/W Notes 1, 2 3 4
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1).
MCM72FB8ML MCM72PB8ML 6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O SUPPLY (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage I/O Supply Voltage Input Low Voltage Input High Voltage Input High Voltage I/O Pins Symbol VDD VDDQ VIL VIH VIH2 Min 3.135 2.375 - 0.3 1.7 1.7 Typ 3.3 2.5 -- -- -- Max 3.465 2.9 0.7 VDD + 0.3 VDDQ + 0.3 Unit V V V V V
RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O SUPPLY (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage I/O Supply Voltage Input Low Voltage Input High Voltage Input High Voltage I/O Pins Symbol VDD VDDQ VIL VIH VIH2 VIH Min 3.135 3.135 - 0.5 2 2 Typ 3.3 3.3 -- -- -- Max 3.465 VDD 0.8 VDD + 0.5 VDDQ + 0.5 Unit V V V V V
VSS
VSS - 1.0 V
20% tKHKH (MIN)
Figure 1. Undershoot Voltage
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML 7
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (0 V Vin VDD) Output Leakage Current (0 V Vin VDDQ) AC Supply Current (Device Selected, All Outputs Open, Freq = Max, VDD = Max, VDDQ = Max) Includes Supply Current from Both VDD and VDDQ CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels) TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels) Clock Running (Device Deselected, Freq = Max, VDD = Max, VDDQ = Max, All Inputs Toggling at CMOS Levels) Static Clock Running (Device Deselected, Freq = Max, VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels) Output Low Voltage (IOL = 2 mA) VDDQ = 2.5 V Output High Voltage (IOH = - 2 mA) VDDQ = 2.5 V Output Low Voltage (IOL = 8 mA) VDDQ = 3.3 V Output High Voltage (IOH = - 4 mA) VDDQ = 3.3 V Symbol Ilkg(I) Ilkg(O) IDDA Min -- -- -- Typ -- -- -- Max 1 1 1700 Unit A A mA 1, 2, 3 Notes
ISB2 ISB3 ISB4
-- -- --
-- -- --
TBD TBD TBD
mA mA mA
4. 5 4, 6 4. 5
ISB5 VOL1 VOH1 VOL2 VOH2
-- -- 1.7 -- 2.4
-- -- -- -- --
TBD 0.7 -- 0.4 --
mA V V V V
4, 6
NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. All addresses transition simultaneously low (LSB) then high (MSB). 3. Data states are all zero. 4. Device is deselected as defined by the Truth Table. 5. CMOS levels for I/O's are VIT VSS + 0.2 V or VDDQ - 0.2 V. CMOS levels for other inputs are Vin VSS + 0.2 V or VDD - 0.2 V. 6. TTL levels for I/O's are VIT VIL or VIH2. TTL levels for other inputs are Vin VIL or VIH.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance Symbol Cin CI/O Min -- -- Typ -- -- Max 16 5 Unit pF pF
MCM72FB8ML MCM72PB8ML 8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V Input Rise/Fall Time (See Figure 3) . . . . . . . . . 1.0 V/ns (20 to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
Pipeline MCM72PB8ML3.5 166 MHz Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Setup Times: Address ADSP, ADSC, ADV Data In Write Chip Enable Hold Times: Address ADSP, ADSC, ADV Data In Write Chip Enable Symbol S bl tKHKH tKHKL tKLKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tADKH tADSKH tDVKH tWVKH tEVKH tKHAX tKHADSX tKHDX tKHWX tKHEX Min 6 2.4 2.4 -- -- 0 1.5 0 -- 1.5 1.5 Max -- -- -- 3.5 3.5 -- -- -- 3.5 6 -- Pipeline MCM72PB8ML4 133 MHz Min 7.5 3 3 -- -- 0 1.5 0 -- 1.5 1.5 Max -- -- -- 4 3.8 -- -- -- 3.8 7.5 -- Flow-Through MCM72FB8ML7.5 117 MHz Min 8.5 3.4 3.4 -- -- 0 2 0 -- 2 2 Max -- -- -- 7.5 3.5 -- -- -- 3.5 3.5 -- Flow-Through MCM72FB8ML8 100 MHz Min 10 4 4 -- -- 0 2 0 -- 2 2 Max -- -- -- 8 3.5 -- -- -- 3.5 3.5 -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 4, 5 4 4, 5 4, 5 4, 5 3 3 Notes N
0.5
--
0.5
--
0.5
--
0.5
--
ns
NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 4. This parameter is sampled and not 100% tested. 5. Measured at 200 mV from steady state.
OUTPUT Z0 = 50 RL = 50 1.25 V
Figure 2. AC Test Load
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML 9
OUTPUT LOAD
OUTPUT BUFFER
TEST POINT
UNLOADED RISE AND FALL TIME MEASUREMENT INPUT WAVEFORM 2.0 0.5 2.0 0.5
OUTPUT WAVEFORM
2.0 0.5 tr tf
2.0 0.5
NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time tr is measured from 0.5 to 2.0 V unloaded. 3. Fall time tf is measured from 2.0 to 0.5 V unloaded.
Figure 3. Unloaded Rise and Fall Time Characterization
MCM72FB8ML MCM72PB8ML 10
MOTOROLA FAST SRAM
PULL-UP VOLTAGE (V) - 0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 I (mA) MIN - 38 - 38 - 38 - 26 - 20 0 0 0 I (mA) MAX - 105 - 105 - 105 - 83 - 70 - 30 - 10 0 0.8 VOLTAGE (V) 2.9 2.5 2.3 2.1
1.25
0 0 - 38 CURRENT (mA) - 105
(a) Pull-Up for 2.5 V I/O Supply
3.6
PULL-UP VOLTAGE (V) - 0.5 0 1.4 1.65 2.0 3.135 3.6 I (mA) MIN - 50 - 50 - 50 - 46 - 35 0 0 I (mA) MAX - 150 - 150 - 150 - 130 - 101 - 25 0 VOLTAGE (V)
3.135 2.8
1.65 1.4
0 0 - 100 - 50 CURRENT (mA) - 150
(b) Pull-Up for 3.3 V I/O Supply
PULL-DOWN VOLTAGE (V) - 0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4 I (mA) MIN 0 0 10 20 31 40 40 40 40 I (mA) MAX 0 0 20 40 63 80 80 80 80 VOLTAGE (V)
VDD
1.6 1.25
0.3 0 0 40 CURRENT (mA) 80
(c) Pull-Down Figure 4. Typical Output Buffer Characteristics
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML 11
MCM72PB8ML PIPELINE READ/WRITE CYCLES
tKHKL tKLKH
tKHKH
K
SA
A
B
C
D
MCM72FB8ML MCM72PB8ML 12
t KHQV BURST WRAPS AROUND Q(A) tKHQX2 Q(B) Q(B+1) Q(B+2) Q(B+3) tGHQZ Q(B) D(C) ADSP, SA SE2, SE3 IGNORED BURST READ BURST WRITE D(C+1) D(C+2) D(C+3) tGLQX Q(D) SINGLE READ
ADSP
ADSC
ADV
SE1
E
W
G
t KHQV
DQx
Q(n)
tKHQZ
tKHQX1
DESELECTED
SINGLE READ
MOTOROLA FAST SRAM
NOTE: E low = SE2 high and SE3 low. W low = SGW low and/or SW and SBx low.
MCM72FB8ML FLOW-THROUGH READ/WRITE CYCLES
tKHKL tKLKH
tKHKH
K
MOTOROLA FAST SRAM
B C D tKHQV BURST WRAPS AROUND tGLQV Q(A) tKHQX1 tKHQX2 Q(B) Q(B+1) Q(B+2) Q(B+3) tGHQZ Q(B) D(C) ADSP, SA SE2, SE3 IGNORED BURST READ BURST WRITE D(C+1) D(C+2) D(C+3) tGLQX Q(D) SINGLE READ
SA
A
ADSP
ADSC
ADV
SE1
E
W
G
DQx
Q(n)
tKHQZ
DESELECTED
SINGLE READ
MCM72FB8ML MCM72PB8ML 13
NOTE: E low = SE2 high and SE3 low. W low = SGW low and/or SW and SBx low.
APPLICATION INFORMATION
STOP CLOCK OPERATION In the stop clock mode of operation, the SRAM will hold all state and data values even though the clock is not running (full static operation). The SRAM design allows the clock to start with ADSP and ADSC, and stops the clock after the last write data is latched, or the last read data is driven out. When starting and stopping the clock, the AC clock timing and parametrics must be strictly maintained. For example, clock pulse width and edge rates must be guaranteed when starting and stopping the clocks. To achieve the lowest power operation for all three stop clock modes, stop read, stop write, and stop deselect: 1. Force the clock to a low state. 2. Force the control signals to an inactive state (this guarantees any potential source of noise on the clock input will not start an unplanned on activity). 3. Force the address inputs to a low state.
MCM72PB8ML PIPELINE STOP CLOCK WITH READ TIMING
K
ADSP
ADDRESS
A1
A2
ADV
DQx
Q(A1)
Q(A1 + 1)
Q(A2)
ADSP (INITIATES BURST READ)
CLOCK STOP (CONTINUE BURST READ)
WAKE UP ADSP (INITIATES BURST READ)
NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL). Best results are obtained if VIL < 0.2 V.
MCM72FB8ML MCM72PB8ML 14
MOTOROLA FAST SRAM
MCM72FB8ML FLOW-THROUGH STOP CLOCK WITH READ TIMING
K
ADSP
ADDRESS
A1
A2
ADV
DQx
Q(A1)
Q(A1 + 1)
Q(A2)
ADSP (INITIATES BURST READ)
CLOCK STOP (CONTINUE BURST READ)
WAKE UP ADSP (INITIATES BURST READ)
NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL). Best results are obtained if VIL < 0.2 V.
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML 15
STOP CLOCK WITH WRITE TIMING
K
ADSC
ADDRESS
A1
A2
WRITE
ADV
DATA IN
D(A1)
D(A1 + 1)
VIH OR VIL FIXED (SEE NOTE)
D(A2)
HIGH-Z DQx ADSC (INITIATES BURST WRITE) CLOCK STOP (CONTINUE BURST WRITE) WAKE UP ADSC (INITIATES BURST WRITE)
NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control lines held in an inactive state.
MCM72FB8ML MCM72PB8ML 16
MOTOROLA FAST SRAM
STOP CLOCK WITH DESELECT OPERATION TIMING
K
ADSC
SE1
DATA IN
VIH OR VIL FIXED (SEE NOTE 1)
HIGH-Z DQx DATA DATA
CONTINUE BURST READ
CLOCK STOP (DESELECTED)
WAKE UP (DESELECTED)
NOTES: 1. While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control lines held in an inactive state. 2. For best possible power savings, the data-in should be driven low.
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML 17
NON-BURST SYNCHRONOUS OPERATION Although this BurstRAM has been designed for PowerPC- based and other high end MPU-based systems, these SRAMs can be used in other high speed L2 cache or memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the MCM72FB8ML or MCM72PB8ML. The burst counter feature of the BurstRAM can be disabled, and the SRAM can be configured to act upon a continuous stream of addresses. See Figures 5 and 6.
CONTROL PIN TIE VALUES (H VIH, L VIL)
Non-Burst Sync Non-Burst, Pipelined SRAM ADSP H ADSC L ADV H SE1 L LBO X
NOTE: Although X is specified in the table as a don't care, the pin must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
H
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 5. Configured as Non-Burst Synchronous Flow-Through SRAM
K
ADDR
A
B
C
D
E
F
G
H
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 6. Configured as Non-Burst Synchronous Pipelined SRAM
MCM72FB8ML MCM72PB8ML 18
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
72FB8 72PB8
XX
X
X
Blank = Trays, R = Tape and Reel Speed for MCM72FB8 (7.5 = 7.5 ns, 8 = 8 ns) Speed for MCM72PB8 (3.5= 3.5 ns, 4 = 4 ns) Package (ML = Multichip Module on Laminate)
Full Part Numbers -- MCM72FB8ML7.5 MCM72FB8ML7.5R MCM72PB8ML3.5 MCM72PB8ML3.5R
MCM72FB8ML8 MCM72FB8ML8R MCM72PB8ML4 MCM72PB8ML4R
PACKAGE DIMENSIONS
MULTICHIP MODULE PBGA CASE 1103B-01
2X
0.2
A1 CORNER
D
C A
209X
0.2 C 0.35 C
4X
(E3) E
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DIMENSIONS D2, D3, E2, AND E3 ARE FOR INFORMATION ONLY. MILLIMETERS MIN MAX 2.00 2.90 0.50 0.70 0.80 1.20 0.60 0.90 25.00 BSC 22.86 BSC 7.14 REF 14.05 REF 1.27 BSC 25.00 BSC 12.70 BSC 7.14 REF 14.05 REF
(E2)
2X
0.2 (D2) B TOP VIEW
5 6 7 8 9 10 11 12 13 14 15 W V U T R P N M L K J H G F E D C B A
(D3)
209X
b 0.30 0.15
M M
ABC A
D1
A2 A A1 SIDE VIEW
DIM A A1 A2 b D D1 D2 D3 e E E1 E2 E3
e
E1 BOTTOM VIEW
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML 19
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 INTERNET: http://motorola.com/sps
MCM72FB8ML MCM72PB8ML 20
MCM72FB8ML/D MOTOROLA FAST SRAM

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